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Technotools (Chestnut CD-ROM)(1993).ISO
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misc_pto
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29ksim
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29k.s
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1987-11-30
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3KB
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145 lines
.title "29K.s -- Test file for 29K-Soft"
;********************************************************************
;the following two equ statements need to be changed if different page
;sizes are to be tested
page .equ 000#h ;0=1k page 100=2k page, 200=4k, and 300=8k
x .equ 0000#h ;0=1k, 0=2k, 2000=4k, 2000=8k
;*********************************************************************
.global main
.nolistmx
.nolistsym
.nolisttx
.nolistix
.include "trap.h"
.include "sr.h"
.include "macro.h"
.list
data .seg data,absolute (5ff8#h + x) ;1 cycle memory
.use data
dmems:
.word 0aa55#h ;data constant for load
.word 06817#h
.word 011ff#h
.word 022cc#h
.word 03399#h
dendm:
fill 01234#h,50
.word 0
.word 0
.word 0
data1 .seg data,absolute (1005ff8#h + x) ; 2 cycle memory
.use data1
d1mems:
.word 0aa55#h
.word 06817#h
.word 011ff#h
.word 022cc#h
.word 03399#h
.word 0
d1endm:
.word 0
.word 0
data2 .seg data,absolute (2005ff8#h + x) ; 3 cycle memory
.use data2
.word 0aa55#h
.word 06817#h
.word 011ff#h
.word 022cc#h
.word 03399#h
.word 0
.word 0
.word 0
code .seg code,absolute 01000#h /* should change back to 1000 later */
.use code
no .equ 20#h ;control byte for load or store no xlate in super mode
yes .equ 0 ;control byte for load or store xlate ok
LOOPCOUNT .equ 100 ; counter through loop
;For now, need to skip supervisor mode so no trap occurs. Later,
;the load stores will be tested in the supervisor mode with PD=1 xlate on
;the PA bit in the load store will control xlate for each instruction
;the tlb table will be zeroed to force tlbmiss when required
;
;;;;;;;;;;;;;;;;;;;;
main:
;;;;;;;;;;;;;;;;;;;;
.listmx
dumpsr 0,3
trap SHOWSYSTIME
trap SHOWSYSTIME ; twice to see how long a trap takes!
/* set up pointers */
const gr50,05ff8#h + x ; should be 05ff8#h + x
consth gr50,00000#h ; high address
/* set up counter */
const gr55,1 ; initialize loop counter
const gr57,LOOPCOUNT
consth gr57,LOOPCOUNT >> 16
mtsrim FS,1 ; set funnel shifter for 1
loop:
call gr5b,copy
cpneq gr56,gr55,gr57 ; test for done !
jmpt gr56,loop
add gr55,gr55,01 ; add one !
trap SHOWSYSTIME
const gr02,200
trap SETTIME
;
dumpsr 8,9
dumpsr 0,3
dumpmem dmems,dendm
trap SHOWTIME
dumpsr 132,132
trap END_SUCCESS ;all tests completed, no errors
;;;;;;;;;;;;;;;
error:
;;;;;;;;;;;;;;;
trap END_FAIL ; failed something
nop
nop
;;;;;;;;;;;;;;;;
copy:
;;;;;;;;;;;;;;;;
load no,gr70,gr50
add gr50,gr50,0 ; increment word address (should be 4 not zero)
extract gr70,gr70,gr50 ; shift in gr50 one bit at a time
jmpi gr5b ; copy complete ok return to main
store no,gr70,gr50 ; delay store in next address
nop ; after jmpi, just in case I forget !
nop ; a couple more to make sure code seg
nop ; is big enough for simulator
.end